The present invention relates to power conversion using a buck topology. More particularly, the invention relates to a buck converter having a synchronous rectifier topology characterized by a combination of low-side switch current sensing and valley current control.
A buck converter functions to step down a high voltage to a lower voltage so that it is compatible with, for example, a CPU on a motherboard for a personal computer. Typically, the buck converter operates using a clock, whereby an inductor is charged or energized during a first portion of a clock cycle ("charging phase") and operates as a current source during the second portion of the clock cycle ("discharging phase").
The inductor is normally placed in series with the load (e.g. CPU) and the capacitor is normally placed in parallel with the load. The inductor reduces the amount of ripple in the inductor current, i.sub.L (t), since the current through an inductor cannot change suddenly. Similarly, the capacitor reduces the amount of ripple on the output voltage, v.sub.o (t), since the voltage across a capacitor cannot change suddenly.
A typical buck converter having a synchronous rectifier topology, operates by commencing the charging phase in response to a clock signal. During the charging phase, the inductor, capacitor and load are coupled to the input voltage. Meanwhile, the inductor current, i.sub.L (t), is monitored, and, when it peaks at a predetermined value, the converter is decoupled from the input voltage and the inductor discharges its energy through the load. Because the separation between the charging and discharging phases is defined at the point in time at which the inductor current, i.sub.L (t), peaks at the predetermined value, this type of buck converter is commonly referred to as a "peak current control" buck converter.
The inductor current, i.sub.L (t), rises and falls linearly according to i.sub.L (t)=.+-.(V.sub.L /L).times.t, where V.sub.L is the voltage across the inductor.
A buck converter can also be characterized as a step-down switch-mode power supply where the average output voltage, V.sub.o,avg, can be shown to be directly proportional to the converter duty cycle, D. In other words, ##EQU1## where, DT=T.sub.on, is the portion of the buck converter clock period during which high-side switch 100 is on.
For efficient power distribution to and throughout a system, the power is typically transmitted at a high voltage and a low current to minimize I.sup.2 R losses. Accordingly, when the power is distributed to the buck converter for step down, the input voltage, V.sub.in, is usually quite high. This means that the only practical way of decreasing the average output voltage, for compatibility with low-power electronic devices (e.g. CPU's that operate from a 1.2 voltage source), is to reduce the duty cycle, D, of the converter operating frequency.
Unfortunately, there is a limit on the extent to which the duty cycle, D, can be reduced before the "peak current control" converter becomes dysfunctional. This limit is approached when the duty cycle, D, becomes so small that it becomes difficult to monitor, measure and use it for loop control. The problem becomes worse at higher frequencies.
Because the "peak current control" buck converter is duty-cycle-limited and frequency-limited, it is incapable of meeting the demands dictated by the advancement of technology. As an example, given an input voltage of V.sub.in =12 volts, a desired output voltage of 1.2 volts, and a clock frequency of 1 MHz, the required duty cycle would be 0.1. With this small duty cycle, however, there would be only 100 nsec of time during which the inductor, capacitor and load would be coupled to the input voltage. Indeed, this length of time is very short and on the order of duration at which the "peak current control" buck converter becomes dysfunctional.
One solution, posed to circumvent the frequency and duty cycle limitations of the "peak current control" converter, contemplates adding "sample" circuitry to the "peak current control" converter, whereby the inductor current, i.sub.L (t), is sampled during the discharging phase. However, because information from this sampling is obtained after the converter has started its discharging phase, the information so obtained can only be utilized during the next clock cycle. Accordingly, with this solution, in addition to sampling the inductor current, i.sub.L (t), further circuitry must be provided to "hold" the current until the next clock cycle. A serious drawback of this solution, therefore, besides the "sample-and-hold" circuitry, which adds complexity to the converter, is that the sample-and-hold mechanism adds a delay or phase shift that threatens the stability of the converter.
What is needed, therefore, is a buck converter architecture that permits current sensing in real time, at high clock speeds and low duty cycles and without the delays and complexities associated with the sample-and-hold technique. Such a solution would comport with the progression towards more efficient power distribution and at the same time provide the ability to achieve a low output voltage that is compatible with state-of-the-art low-voltage electronic devices.